This invention relates to a semiconductor circuit device which comprises a differential amplifier circuit.
A reference voltage generation circuit is well known in the art as an example of a semiconductor circuit device comprising a differential amplifier circuit. In the case that the reference voltage generation circuit is implemented by a semiconductor integrated circuit, the reference voltage generation circuit comprises a semiconductor substrate, first through third resistors which are formed on the semiconductor substrate, and the differential amplifier circuit which is formed on the semiconductor substrate. The differential amplifier circuit comprises first and second input terminals and an output terminal. The first resistor is connected between a signal input terminal and the first input terminal through a first wiring pattern. The first resistor and the first wiring pattern serve as a signal input line. A second resistor is connected between the output terminal and the second input terminal through a second wiring pattern. Furthermore, the second input terminal is grounded through the third resistor. The first input terminal is supplied with an input signal through the first resistor and has a first input electric potential or voltage. The second input terminal has a second input electric potential or voltage.
The reference voltage generation circuit amplifies a differential voltage between the first and the second input voltages and delivers an amplified signal to the output terminal as an output signal having a predetermined reterence voltage. The second resistor serves as a feedback resistor to feedback the output signal to the second input terminal. Therefore, the second resistor and the second wiring pattern serve as a feedback line. The third resistor serves as a voltage dividing resistor.
In the meantime, the reference voltage generation circuit is inevitable to have first and second parasitic capacitors. The first parasitic capacitor is formed between the signal input line and the semiconductor substrate, in particular, between the first resistor and the semiconductor substrate. The first parasitic capacitor has a first capacitance value. Similarly, the second parasitic capacitor is formed between the feedback line and the semiconductor substrate, in particular, between the second resistor and the semiconductor substrate. The second parasitic capacitor has a second capacitance value. The first and the second capacitance values are different from one another. The first and the second input voltages are influenced by the first and the second parasitic resistors, respectively. If an outer noise intrudes into the reference voltage generation circuit, the first and the second input voltages individually vary in amplitude with a time lag because the first and the second capacitance values are different from one another. In this event, the output signal has a large variation of amplitude. This means that the reference voltage generation circuit is hard to generate the output signal having the predetermined reference voltage.